Learn computer architecture by running the simulator
curl -fsSL https://studyriscv.com/riscvsim.sh | sh
Paste this in your terminal, or open the simulator
Run assembly. See the machine state.
Run a RISC-V program instruction by instruction. Watch registers, memory, and the program counter change.
riscvsim demo
Browse the instruction reference →
$ studyriscv demo Loading add.s... Assembling program... Running simulator... addi x3, x0, 3 addi x4, x0, 4 add x5, x3, x4 x3: 0 -> 3 x4: 0 -> 4 x5: 0 -> 7 ✓ program complete
Start in the terminal. Continue in the browser.
Run a program locally, then open the browser simulator to inspect code, registers, memory, execution trace, and pipeline state visually.
riscvsim serve
Registers
x33
x44
x57
x60
Memory
0x0013 01 30 00
0x0413 02 40 00
0x08b3 82 41 00
pc
→
0x0000000c
writeback
What you will understand
- How RISC-V instructions execute
- Why registers change
- How memory is read and written
- What the program counter does
- How simple assembly programs are debugged
- How CPU pipeline stages fit together
