The easiest way to learn RISC-V instructions is to group them by what they do to the machine: arithmetic changes register values, loads and stores move data, branches redirect control flow, and stack-oriented code preserves execution context. StudyRISC-V lets you inspect each category live in the browser.
Fast instruction-set orientation, opcode examples, and internal links to the broader reference docs, beginner guide, and assembly tutorial.
Most RISC-V instructions become easier once you read them as small state transitions.
Identify the destination register or memory location, then identify the source operands,
and finally ask whether the program counter changes. This framing works for arithmetic
instructions like add, memory instructions like lw, and control
instructions like beq or jal. Once you apply that habit
consistently, unfamiliar mnemonics stop being opaque.
The categories below cover the instructions most students touch first. They are also the ones that show up repeatedly in StudyRISC-V lessons, problems, and the opcode explorer on the landing page.
add, addi, sub, and, or, xorThese instructions compute a value from registers or an immediate and write the result to a destination register. They are the backbone of counters, address formation, and boolean masking.
lw, lh, lb, sw, sh, sbLoads read from memory into a register. Stores write from a register into memory. These instructions make the load-store model concrete.
beq, bne, blt, jal, jalrThese instructions redirect execution. They define loops, conditions, function calls, and returns by changing the next program counter value.
addi is often the first instruction students truly internalize, because it
can initialize registers, advance pointers, and update counters. add and
sub extend that same pattern to two-register arithmetic. Instructions like
sll, srl, and sra add bit shifting, while
andi, ori, and xori support masking and toggling.
lw and sw are usually the first memory instructions you need,
but the byte and halfword variants matter whenever layout and sign extension become part of
the problem. These instructions are easiest to learn by tracing the effective address and
checking memory after each step in the simulator.
The branch family controls loops and conditionals. beq and bne
compare equality, while blt, bge, bltu, and
bgeu distinguish signed from unsigned comparisons. This distinction matters a
lot more once values stop being purely positive.
addi a0, x0, 5
addi a1, x0, 7
add a2, a0, a1
sw a2, 0(sp)
lw t0, 0(sp)
In five lines, you see register initialization, arithmetic, a store into memory, and a
load back into a register. If you inspect this sequence in the
StudyRISC-V simulator, you can verify the register writes, the
memory word at the stack pointer, and the exact moment the loaded value reappears in
t0.
jal and jalr deserve special attention because they underpin
function calls and returns. jal writes the return address and jumps to a
label. jalr computes the target from a register, which is why returning via
ra works. Once you pair those instructions with stack saves and restores, you
have the core mechanism behind procedure calls in RISC-V.
This is also where instruction meaning becomes architectural behavior. A call is not just a jump. It is a saved continuation point, a new stack frame, and a contract about which registers survive the call. That is why instruction reference pages are useful, but a simulator remains necessary for deep understanding.
Use this page when you need a quick map of the common RISC-V instructions. Use the assembly tutorial for full worked patterns, the beginner guide for conceptual sequencing, and the docs for deeper reference sections on memory, calling convention, and simulator controls. Then reinforce the instruction set in problems or checkpoints where the opcodes have to cooperate inside a larger solution.
Open StudyRISC-V to trace arithmetic, memory, and branch instructions one step at a time with register inspection and visual learning tools.