RISC-V 5-stage pipeline simulator with forwarding, hazard, and branch-prediction visualization
Keyboard shortcuts
On Step, an instruction enters at IF (fetch) and moves one stage right each cycle: IF → ID → EX → MEM → WB.
Step / backRight Left
Run / pauseSpace
ResetEsc
Ready
Output
cycle 0pc 0x00000000
Registers
Memory
SourceRISC-V (32-bit)
not compilable
C pseudocode