Conquer the computer.

Dive into computer architecture, low-level languages, hardware, and more.
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Try the simulator

C/C++/Rust RISC-V Digital Logic Multithreading Cache hierarchy Compilers Boolean algebra Pipelining Branch prediction Hazards Virtual memory Instruction sets Parallel computing Microarchitecture Number systems Floating point Combinational circuits Sequential circuits State machines Interrupts I/O systems Operating systems GPU architecture Out-of-order execution Von Neumann architecture Register files

Run assembly. See the machine state.

Run a RISC-V program instruction by instruction. Watch registers, memory, and the program counter change.

Run it with no arguments to open the interactive session, then drive it with slash commands.

riscvsim

Browse the instruction reference →

$ riscvsim

╭─ riscvsim 0.1.0 ─────────────────────────╮
│                                          │
│  RV32IM · 5-stage pipeline               │
│                                          │
│  /help    list every command             │
│  /demo    run a sample program           │
│  /serve   open it in the browser         │
│                                          │
╰──────────────────────────────────────────╯

> /demo

Loading add-forward.s...
Assembling program...
Running simulator...

addi x1, x0, 5
addi x2, x1, 3
add  x3, x2, x1

x1: 0 -> 5
x2: 0 -> 8
x3: 0 -> 13

✓ program complete

Start in the terminal. Continue in the browser.

Run a program locally, then open the browser simulator to inspect code, registers, memory, execution trace, and pipeline state visually.

Serve a file directly, or type /serve inside the interactive session to hand off whatever you have loaded.

riscvsim serve program.s

localhost:5173 / add.s

Registers

x33

x44

x57

x60

Memory

0x0013 01 30 00

0x0413 02 40 00

0x08b3 82 41 00

pc → 0x0000000c writeback

What you will understand

How RISC-V instructions execute
Why registers change
How memory is read and written
What the program counter does
How simple assembly programs are debugged
How CPU pipeline stages fit together

Open by design.

No black box. Free for everyone.

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