Built for engineers who want to understand the machine.
Computer engineering principles are some of the most beautiful ideas in all of technology. StudyRISC-V exists to make them accessible.
The tools weren't there.
If you want to learn Python, you have Jupyter notebooks, hundreds of interactive tutorials, and tools that meet you where you are. If you want to learn RISC-V assembly, the foundation of modern processor design, you get a dense textbook and a simulator that looks like it was built in 2003.
That gap bothered me. The concepts aren't hard. The execution of a single
addi instruction, the way a function call builds a stack frame, the elegance
of a load-store architecture, these ideas are genuinely beautiful once you see them clearly.
The tools just weren't showing them clearly.
I built StudyRISC-V because I was frustrated taking ECE 2035 at Georgia Tech and watching students struggle not with the concepts, but with the tooling. Venus works. RARS works. But neither of them makes you feel like you understand what the CPU is actually doing.
Satchit Seth
Computer Engineering · Georgia Tech · CompE + AI/ML
I'm a Computer Engineering student at Georgia Tech focusing on Distributed Systems, Software Design, and Systems Architecture.
StudyRISC-V started because I was frustrated taking ECE 2035 (Assembly and C language) and watching students struggle not with the concepts, but with the tooling. Venus works. RARS works. Neither makes you feel what the CPU is actually doing. I built the simulator I wished existed.
Welcome to StudyRISC-V.
The simulator core is written in Rust, compiled to WebAssembly via wasm-pack, and runs entirely in your browser. No server processes your assembly. The backend (auth, saved programs) runs on AWS via a CDK-managed stack.