RISC-V 5-stage pipeline simulator with forwarding, hazard, and branch-prediction visualization
riscvsim 0.1.0 | RV32IM 5-stage pipeline simulator
browser session | ready
Keyboard shortcuts
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Ready
Output
cycle 0pc 0x00000000
Registers
Memory
SourceRISC-V (32-bit)
C is compiled into executable RV32IM assembly. Assembly-to-C output is illustrative pseudocode for reading and is not compilable C. The compiler supports integer variables and arrays, arithmetic, control flow, functions, and recursion. It does not support pointers, structs, globals, strings, floats, or the standard library.
C pseudocode (illustrative, not compilable)